Adaptive DROIC Equipped with Pixel-Level Multiple SS-ADC for High-Resolution Microbolometer IRFPAs

2.1 Basic concepts

Fig. 1 (a) shows a schematic of the unit circuit used to implement a pixel-level SS-ADC. This circuit includes an integrator for converting the input current (I_SIG) into a voltage, a comparator for comparing the integrated voltage (V(C_INT)) with a reference voltage (V_TH) to measure the size of the input, and a memory component for storing the digital conversion value. Here,f_RST, V_RST, and C_INT are the reset signal, reset voltage, and integration capacitor, respectively. Fig. 1 (b) displays the V(C_INT) waveform during standard SS-ADC operation, showing example waveforms for two different input currents (I_SIG1 and I_SIG2). In conventional SS-ADCs, V(C_INT) is maintained at the post-maximum integration time (T_m), and A/D conversion is conducted using a ramp signal. In scenarios where a high current such as I_SIG1 reaches the saturation voltage (V_SAT) before T_m, it cannot be reliably converted into a digital value, thus diminishing the DR. A solution to this limitation involves multiple samplings. If V(C_INT) surpasses the reference value at time T₀ before T_m, it is held, as shown by the dotted line in Fig. 1 (b), and the SS-ADC is carried out after T_m. Depending on when V(C_INT) is maintained, subsequent adjustments are necessary for the digital value. By employing multiple integrations that dynamically adjust the integration time based on the signal intensity, accurate results can be achieved even for large inputs, thereby significantly enhancing the DR. However, this method leads to higher power consumption and complicates accurate A/D conversion owing to changes in the held V(C_INT) value caused by the leakage current.

Fig. 1.

Pixel-level SS-ADC: (a) simplified schematic, (b) timing diagram for conventional SS-ADC, and (c) timing diagram for proposed ADC.

Fig. 1 (c) displays the timing diagram for the proposed multiple SS-ADC, as depicted in Fig. 1 (a). The maximum integration time, T_m, is subdivided as shown in Fig. 1 (c), and V(C_INT) is compared with V_TH, defined as 0.5(V_SAT + V_RST), at intervals of 2^-nT_m (n = 4, 3, 2, 1, 0). If V(C_INT) exceeds V_TH at any comparison point, it is held and SS-ADC is performed using a ramp signal. For lower inputs such as I_SIG2, which do not reach the reference voltage by T_m, the SS-ADC proceeds using a ramp signal based on V_TH. This method enhances the DR by dynamically adjusting the conversion gain according to the signal intensity and significantly reduces the power consumption by deactivating all analog circuits immediately after the digital result is captured.

2.2 Unit-cell circuit

Fig. 2 shows a schematic of the unit-cell circuit for the proposed pixel-level ADC. The integrator and comparator are configured using amplifiers A₁ and A₅, respectively. Amplifiers A₁ and A₂ are folded-cascode and two-stage amplifiers, respectively, and both amplifiers have an average power consumption of less than 100 nW. The two latches control the circuit based on the comparator outputs, and a 12-bit SRAM stores the digital conversion results. A 12-bit counter and V_R control circuit, shared row-by-row outside the unit-cell array, generate globally synchronized signals. A bias current suppression method is employed to eliminate unnecessary bias current (I_B) from the image and integrate only the signal current (I_SIG) [24,25], thus reducing noise by ensuring an adequate integration time within the limited capacitance (C_INT) owing to the constrained pixel area. Capacitor C_CDS enables correlated double-sampling (CDS) operations [26-28]. The comparator output clarity is enhanced by an inverter and a level shifter, which ensure a proper logic-level understanding. To minimize the fall time of the comparator output, 0.5V_DD is used as the low-side power for the inverter, aligning its logic threshold voltage closer to V_DD.

Fig. 2.

Schematic of the unit cell circuit for the proposed multiple SS-ADC.

Fig. 3 presents a detailed circuit diagram of the two latches depicted in Fig. 2, and Fig. 4 illustrates the timing diagram for the operation shown in Fig. 2. Given the extremely small pixel pitch of the target bolometer array in this study, incorporating the circuit shown in Fig. 2 within a single pixel is challenging. Consequently, the adjacent 4 × 4-pixel bolometers share a unit-cell circuit in a time-division manner, as shown in Fig. 2. The timing diagram in Fig. 4 applies to one pixel and accounts for 1/16 of the frame time, which is equivalent to 2.08 ms at a 30 Hz frame rate.

Fig. 3.

Detailed diagrams of the two latches in Fig. 2: (a) Latch 1 and (b) Latch 2.

Fig. 4.

Timing diagram for the proposed ADC shown in Fig. 2.

Initially, the output voltage of the integrator (V_X) and input voltage of the comparator (V_Y) are both set to V_RST owing to the f_RST signal, and the outputs of each latch, $$ \overline{L{1}_{OUT}}$$ and $$ \overline{L{2}_{OUT}}$$, are initialized to the Logic 1 value. V_Y, which represents the integral of I_SIG, increases in response to the f_SW signal, which adjusts the maximum integration time. The comparator and Latch 1 inputs are enabled by the f_EN1 signal to compare V_Y with the comparator's reference voltage, V_R (= V_TH), at 2^-nT_m. If V_Y is less than V_TH at a specific comparison time, I_SIG continues to integrate. However, if V_Y exceeds V_TH, $$ \overline{L{1}_{OUT}}$$ switches to Logic 0 and remains in this state until the next reset. At this point, when V_Y is held, V_R is adjusted to V_RAMP, and Latch 2 is activated by the f_EN2’ signal. The held V_Y signal is compared with ramp signal V_RAMP under the f_EN2 signal; when V_RAMP matches V_Y, $$ \overline{L{2}_{OUT}}$$ switches to Logic 0, maintaining this state until the next reset. Simultaneously, the digital value from the 12-bit counter synchronized with V_RAMP, is stored in the 12-bit SRAM, finalizing the digital conversion, and the power to the integrator and comparator is terminated. If V_Y does not reach V_TH by T_m, V_Y is maintained at a constant value by f_SW, latch 2 is activated by the f_LAST signal, and the SS-ADC operation proceeds using V_TH converted to a ramp signal. After the integration and A/D conversion, a digital signal is transmitted to the column multiplexer outside the unit-cell circuit array via a row-by-row f_READ signal.

2.3 Full readout integrated circuit

Fig. 5 presents a simplified block diagram of the comprehensive DROIC for the proposed multiple SS-ADC. Given that each 4 × 4 bolometer array shares a single unit- cell circuit, a 160 × 128 array of unit-cell circuits is needed to form a 640 ´ 512 infrared focal plane array (IRFPA). The system includes a row scan circuit to generate row-by-row control signals and reference signal generator that supplies reference voltages such as the V_R signal for the unit-cell circuit. Additionally, a suppression circuit, column-level 12-bit ADC, and digital-to-analog converter (DAC) are employed to produce and retransmit the bias information of each bolometer for precise bias suppression. A dark sensor establishes a reference point for bias suppression and column multiplexer sequentially outputs the digital values transmitted from each unit-cell circuit.

Fig. 5.

Block diagram of the complete DROIC.

3.1 Operation of the unit cell circuit

Fig. 7 shows the operational-waveform simulation results for the proposed pixel-level ADC with three different input currents. For input current I_SIG = 0.14 nA, the waveform at the conclusion of the digital conversion process is magnified and displayed as a dotted rectangle. When I_SIG = 6.5 nA, V_Y exceeds V_R (V_TH) during the first comparison with f_EN1, prompting V_Y to be held, whereas V_R switches to ramp signal V_RAMP controlled by L1_OUT. The SS-ADC process then proceeds with f_EN2 set to Logic 1. When V_R (V_RAMP) matches V_Y, the digital conversion value is stored by L2_OUT. The stored digital value is transmitted to the column multiplexer using the f_{READ_1} signal. For I_SIG = 0.82 nA, V_Y first exceeds V_TH during the fourth comparison with f_EN1, leading to the holding of V_Y and subsequent execution of the SS-ADC operation after this comparison.

Fig. 7.

Simulation results showing operational waveforms for the proposed pixel-level ADC.

When I_SIG = 0.14 nA, V_Y does not surpass V_TH before the maximum integration time, T_m, elapses. As a result, L1_OUT remains unchanged, and V_Y is held by f_SW after integration until T_m. The SS-ADC operation then proceeds based on the f_EN2 and f_LAST signals. As depicted in the magnified section within the dotted rectangle, the ramp signal is a step waveform produced by the global 12-bit counter and DAC. Once ramp signal V_R reaches the maintained V_Y, the output of the comparator (A_{2_OUT}) transitions slowly from a high to low voltage. However, L2_OUT responds quickly within one clock cycle, enabled by an inverter designed with a high logic threshold voltage at the A_{2_OUT} terminal.

By dynamically adjusting the integration time based on the input signal intensity, the proposed pixel-level ADC achieves a wide DR and enhanced SNR for smaller inputs requiring sufficient integration time. Additionally, the accuracy of the A/D conversion is improved by implementing the ADC immediately after integration, and the average power consumption is significantly reduced by deactivating the power to the analog circuit immediately after the A/D conversion.

3.2 Noise characteristics and power consumption

In a readout circuit designed for high-quality infrared imaging, the noise characteristics that determine the minimum recognizable signal level are of paramount importance. The primary sources of noise in a microbolometer IRFPA are thermal and flicker noise, which can be reduced by providing sufficient integration time for the input current [4,5]. Therefore, a pixel-level readout circuit that can provide a sufficient integration time is advantageous. This necessitates the use of a large integration capacitor within the confined space of the pixel area, along with the integration of the input current after removing unnecessary bias current. For portable micro-IR cameras, where environmental conditions can change swiftly, the readout circuit must effectively process both small and large input signals. The ability to handle such varying input signals is quantified by the DR, which is defined as the ratio of the maximum available signal to the minimum recognizable signal.

Fig. 8 displays the estimated SNR characteristics of the proposed pixel-level multiple SS-ADC, which is designated as <A>, comparing it with the SNRs of other methodologies. In this figure, <A> represents the proposed ADC, while the remaining data pertain to the conventional SS-ADC after integration time. The methods labeled <B> and <B'> are designed with limited integration times to align the maximum input range with that of <A>. Notably, Method <B'> does not incorporate a bias-suppression circuit. In Method <C>, the input range is restricted to equalize the maximum integration time to that of <A>. The proposed ADC demonstrates superior SNR characteristics across a wide input range by employing an optimal integration time customized to the input intensity.

Fig. 8.

Comparison of SNR characteristics with current input.

Fig. 9 shows a comparison of the DR and power consumption per pixel values for the four methods shown in Fig. 8. Method <C> consumes a large quantity of power because the analog circuit is activated for a long integration time regardless of the input intensity. Methods <B> and <B'> suffer from a trade-off between power consumption and noise characteristics because of their limited integration times. The proposed ADC significantly reduces the average power consumption by optimizing the operational duration of the analog circuit in response to the input intensity.

Fig. 9.

Comparison of DR characteristics and power consumption.

Table 2 presents a performance comparison between the proposed ADC and alternative methods. The design of the DROIC is strongly influenced by the specifications of the IRFPA. Consequently, the pixel-level ADC of the uncooled IRFPA is mainly selected for the comparative analysis. The maximum integration time, T_m, serves as an indicator of the noise level, and the power consumption per pixel is normalized against the frame rate. A PFM-based pixel-level ADC that requires multiple comparisons to achieve a wide DR consumes considerable power [20]. This problem can be addressed by employing a PFM-based two-stage ADC or extended-counting ADC (EC-ADC) [29]. However, an EC-ADC also has limitations in reducing the power consumption because the integration time remains constant regardless of the input signal intensity. While column-level (CL) ADCs are simpler to design than pixel-level ADCs, achieving low-noise characteristics is challenging because T_m is constrained by the array size [30].

Table 2.

Performance comparison.

3.3 Multiple modes for adaptive operation

The proposed DROIC offers multiple operational modes with adaptive characteristics that respond to the surrounding environment. Because each 4 × 4 bolometer array shares a single unit-cell circuit, the spatial resolution can be readily adjusted. Depending on ambient conditions, reducing the spatial resolution can enhance the DR, speed, and noise characteristics. Table 3 summarizes the four modes and their respective parameters.

Table 3.

Four modes and their parameters.

Fig. 10 compares the DR and power consumption values across the four modes. The wide-DR (WDR) mode enhances the DR by decreasing the spatial resolution, prolonging the time allocated to each pixel, and further subdividing the integration time. The fast mode increases the frame rate by reducing the spatial resolution. However, elevating the frame rate beyond 50 Hz is impractical owing to bolometer constraints. In scenarios in which the input signal is minimal, it is crucial to extend the integration time to reduce noise. An adequate integration time can be ensured by reducing both the spatial resolution and frame rate in the low-noise mode. Although the low-noise mode exhibits a diminished DR owing to its restricted input range and elevated power consumption owing to prolonged integration times, it significantly improves the SNR characteristics for small inputs, as illustrated in Fig. 11.

Fig. 10.

DR and power consumption comparisons across four operational modes.

Fig. 11.

SNR characteristics for small inputs in low-noise mode.