
A D-Band Neutralized Upconversion Mixer With Enhanced Stability and Conversion Gain
ⓒ The Korean Sensors Society
This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (https://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
This paper presents a 140-GHz double-balanced Gilbert-cell upconversion mixer in a 28-nm CMOS process for radar sensing and communication systems. The proposed mixer employs capacitive neutralization in the transconductance (Gm) stage and an interstage matching network between the Gm and mixing stages. The neutralization technique suppresses the feedback caused by the gate-to-drain capacitance, while the interstage matching network improves power transfer between the two stages. The mixer is designed for the RF upconversion stage of a 140-GHz D-band sliding-IF transmitter and supports a 60-GHz IF input. Simulation results show that the proposed circuit remains unconditionally stable operation over the simulated frequency range. The mixer achieves a conversion gain of 4.6 dB and an output 1-dB compression point of -5.4 dBm with a DC power consumption of 8.3 mW. Compared with the conventional Gilbert-cell architecture, the conversion gain and output 1-dB compression point are improved by approximately 3 and 1.2 dB, respectively.
Keywords:
D-band, Upconversion, Gilbert-cell mixer, Neutralization capacitor, Core stage matching1. INTRODUCTION
The rapid evolution of modern sensing and communication systems has led to an increasing demand for higher sensing resolution, wider operating bandwidths, and higher data rates. In particular, emerging applications such as contactless vital-sign monitoring and integrated sensing and communication (ISAC) increasingly rely on millimeter-wave and sub-terahertz frequency bands. Among these frequency ranges, the D-band is particularly attractive for both radar sensing and high-data-rate communications, offering short wavelengths for high phase sensitivity to small target displacements and a wide available bandwidth for fine range resolution and high-capacity wireless links [1,2]. Accordingly, the design of stable and power-efficient D-band transceivers has become increasingly important for future sensing and communication systems.
In a transmitter, an upconversion mixer plays a crucial role in translating a baseband signal to the desired radio frequency (RF) band. In a conventional transmitter architecture, the baseband signal is directly converted to the target RF frequency. However, at sub-terahertz frequencies, the generation of a high-frequency local oscillator (LO) signal becomes increasingly challenging and generally requires substantial DC power consumption, thereby degrading the overall efficiency of the transceiver. To address this limitation, a sliding-IF transmitter architecture employing multiple frequency-conversion stages was proposed in [3]. In this architecture, the LO signal is generated at a relatively low-frequency, and the desired RF signal is obtained through two frequency-conversion stages, thereby alleviating the power and implementation challenges associated with the direct generation of a sub-terahertz LO signal. The architecture shown in Fig. 1(b) is based on the same sliding-IF concept. For the frequency plan adopted in this work, a 60-GHz IF signal is generated in the first stage and mixed with an 80-GHz LO to produce the desired 140-GHz RF output, where fRF = fIF + fLO = 60 + 80 = 140 GHz. Since the two LO signals are the third and fourth harmonics of a 20-GHz signal, respectively, both can be derived from a single 20-GHz VCO. In such an architecture, the second-stage upconversion mixer must process a relatively high IF signal. However, previously reported D-band upconversion mixers generally show a trade-off between high-IF operation and conversion gain or output linearity.
In this work, a Gilbert-cell-based upconversion mixer supporting a 60-GHz IF input is designed for a 140-GHz D-band sliding-IF transmitter. The proposed mixer employs a capacitive neutralization technique to mitigate the gain degradation and stability deterioration caused by the gate-to-drain capacitance (CGD) of the transconductance (Gm) stage. In addition, an interstage impedance matching network is introduced between the high-frequency Gm stage and the LO-driven mixing stage to improve power transfer between the two stages and alleviate gain compression, thereby enhancing output linearity.
The remainder of this paper is organized as follows. Section II describes the conventional Gilbert-cell architecture and discusses its limitations. It then presents the proposed upconversion mixer, which mitigates these limitations through capacitive neutralization and interstage impedance matching. Section III presents the simulation results for stability, conversion gain, and linearity and compares the proposed design with the conventional architecture. Finally, Section IV summarizes the main findings and concludes this work.
2. DESIGN OF THE PROPOSED GILBERT-CELL FREQUENCY UPCONVERTER
Fig. 2 illustrates the conventional Gilbert-cell mixer architecture. The active mixer provides conversion gain and consists of a transconductance (Gm) stage (M5, M6) and a mixing stage (M1~M4). Owing to its circuit symmetry and high port-to-port isolation, the double-balanced architecture, in which both the input and output signals are differential, provides stable operation and suppresses undesired signal feedthrough. Although the differential mixing quad is inherently stable owing to its symmetric mixing operation, the Gm stage is structurally equivalent to a conventional common-source amplifier and therefore requires a separate stability enhancement technique. In particular, the gate-to-drain capacitance of the Gm stage transistors forms a feedback path between the input and output, which may lead to oscillation at high frequencies. Furthermore, as the operating frequency increases, signal leakage and power loss caused by the parasitic capacitance between the Gm and mixing stages become more significant. Therefore, an interstage impedance matching network is required to enhance the power transfer from the Gm stage to the mixing stage and alleviate power compression caused by impedance mismatch.
To address these two issues, this work employs a capacitive neutralization technique and an interstage impedance matching network as shown in Fig. 3. First, capacitive neutralization is applied to enhance the stability of the Gm stage [4]. As the transistor size increases, the associated parasitic capacitances also increase, and their feedback effects become more pronounced at higher frequencies, potentially resulting in positive feedback. A neutralization capacitor introduces an opposing coupling path that cancels the feedback-induced signal leakage. The resulting neutralization condition is expressed in (1) [4].
| (1) |
| (2) |
In (1) and (2), CGD denotes the gate-to-drain capacitance of the transistor, whereas Cx represents the neutralization capacitance. As Cx approaches CGD, the equivalent capacitance between the input and output terminals of the transistor approaches zero, thereby improving the input-to-output isolation. Consequently, the stability of the circuit is enhanced. In practice, however, the optimum Cx may differ from the nominal CGD because the effective gate-to-drain capacitance is affected by layout parasitics. Therefore, Cx should be optimized at the target operating frequency to minimize the effective feedback.
Although capacitive neutralization enhances the stability of the Gm stage, impedance mismatch between the Gm and mixing stages still limits the conversion gain. Therefore, an interstage impedance matching network is employed to maximize power transfer. The real part of the interstage impedance is optimized by adjusting the transistor-size ratio between the two stages. The imaginary part is compensated using an inductor that resonates with the parasitic capacitance at the target operating frequency, thereby improving signal transfer between the Gm and mixing stages. By improving power transfer between the two stages, the matching network also mitigates gain compression and improves the output 1-dB compression point.
The input and output matching networks are implemented using transformer-based baluns at the IF, LO, and RF ports. These transformers interface the differential mixer core with single-ended 50Ω GSG pads. At the IF and LO inputs, the transformers perform single-ended-to-differential conversion and impedance transformation for the Gm and switching stages, respectively. The center taps of their secondary windings provide the gate-bias voltages required by the Gm and switching transistors without interfering with the differential input signals. At the RF output, the transformer combines the differential output signals and transforms the output impedance to 50 Ω. The center tap of its primary winding is connected to the DC supply voltage (VDD).
For the proposed design, the IF, LO, and RF transformers are designed with equal primary and secondary inductances (Lp=Ls) of 180, 110, and 28 pH, respectively, with a coupling coefficient k of 0.65 for all three transformers. These parameters are optimized at their respective operating frequencies while accounting for approximately 30 fF of device, interconnect, and pad parasitics to reduce port reflections.
3. SIMULATION RESULTS
Fig. 4 shows the simulated stability factor of the Gm stage. For the conventional Gilbert-cell architecture, the stability factor remains below unity over the entire frequency range from DC to 300 GHz and exhibits a minimum value of 0.4 at 50 GHz, indicating that the circuit may become unstable under certain source or load impedance conditions. In contrast, the proposed architecture achieves a minimum stability factor of 1.1 at DC, while maintaining a value greater than unity over the entire frequency range. These results demonstrate that the proposed circuit is unconditionally stable throughout the simulated frequency range.
Fig. 5 presents the simulated linearity and conversion gain characteristics. Under the same DC power consumption, the proposed architecture improves the output 1-dB compression point by approximately 1.2 dB and the conversion gain by approximately 3 dB compared with the conventional Gilbert-cell architecture. The proposed mixer achieves a conversion gain of 4.6 dB and an output 1-dB compression point of −5.4 dBm.
Table 1 summarizes the performance of the proposed mixer and compares it with previously reported D-band upconversion mixers. The proposed mixer supports a 60-GHz IF while maintaining DC power consumption comparable to low-IF designs ([5-7]), with competitive conversion gain and improved OP1dB. It also outperforms the previously reported high-IF design ([8]) in conversion gain and output linearity.
4. CONCLUSIONS
In this work, a D-band upconversion mixer is designed in a 28-nm CMOS process to improve power transfer between the Gm and mixing stages while employing capacitive neutralization. The impedance interaction between the two stages is properly controlled through transistor sizing and inductive compensation, thereby mitigating impedance mismatch, improving power transfer, and alleviating gain compression. Meanwhile, capacitive neutralization enhances the stability of the Gm stage while further improving the conversion gain. Compared with the conventional Gilbert-cell architecture, the proposed mixer achieves improved stability, conversion gain, and output 1-dB compression point without introducing additional active stages. These results demonstrate a simple and effective approach to enhancing D-band mixer performance with minimal circuit complexity.
Acknowledgments
This research was supported by Kyungpook National University Research Fund, 2024.
REFERENCES
-
S. Park, A. Hemelhof, Y. Zhang, G. Gramegna, P. Wambacq, D-band broadband high-efficiency frequency doubler and quadrupler with optimal load impedance control in 250-nm InP DHBT, IEEE Trans. Microw. Theory Tech. 74 (2026) 2475–2485.
[https://doi.org/10.1109/TMTT.2025.3644859]
-
S. Park, D.-W. Park, K. Vaesen, A. Kankuppe, S. Sinha, B. van Liempd, et al., A D-band low-power and high-efficiency frequency multiply-by-9 FMCW radar transmitter in 28-nm CMOS, IEEE J. Solid-State Circuits 57 (2022) 2114–2129.
[https://doi.org/10.1109/JSSC.2022.3157643]
-
S.P. Singh, M.J. Nokandi, T. Rahkonen, A. Pärssinen, On the use of sub-harmonic mixer in sliding-IF architecture for mm-Wave/THz transceivers, Proceedings of the 2nd 6G Wireless Summit (6G SUMMIT), Levi, Finland, 2020, pp. 1–4.
[https://doi.org/10.1109/6GSUMMIT49458.2020.9083758]
-
H. Asada, K. Matsushita, K. Bunsen, K. Okada, A. Matsuzawa, A 60 GHz CMOS power amplifier using capacitive cross-coupling neutralization with 16% PAE, Proceedings of the 6th European Microwave Integrated Circuit Conference (EuMIC), Manchester, UK, 2011, pp. 554–557.
[https://doi.org/10.23919/EuMC.2011.6101808]
-
C.J. Lee, J.-S. Kang, C.S. Park, A D-band low-power gain-boosted up-conversion mixer with low LO power in 40-nm CMOS technology, IEEE Microw. Wireless Compon. Lett. 27 (2017) 1113–1115.
[https://doi.org/10.1109/LMWC.2017.2763753]
-
Y. Lei, G. Su, Z. Su, X. Liu, L. Sun, A D-band up-conversion mixer with 7.5 dB gain and 40 dB LO-RF isolation in 65-nm CMOS technology, Proceedings of the 11th UK-Europe-China Workshop on Millimeter Waves and Terahertz Technologies (UCMMT), Hangzhou, China, 2018, pp. 1–3.
[https://doi.org/10.1109/UCMMT45316.2018.9015737]
-
T. Huang, P. Hetterle, A. Engelmann, F. Probst, A.-M. Schrotz, R. Weigel, et al., A 1.7 dBm OP1dB D-band up-conversion mixer utilizing adaptive back-gate bias in 22 nm FDSOI, Proceedings of the IEEE Asia-Pacific Microwave Conference (APMC), Bali, Indonesia, 2024, pp. 525–527.
[https://doi.org/10.1109/APMC60911.2024.10867429]
-
S. Yang, Analysis of high frequency behaviors of the self-biased TIA stage and implementation of an up-conversion mixer in millimeter-wave/terahertz band, IEICE Electron. Express 19 (2022) 20210562.
[https://doi.org/10.1587/elex.19.20210562]





