[ Article ]

JOURNAL OF SENSOR SCIENCE AND TECHNOLOGY - Vol. 33, No. 3, pp.147-151

ISSN: 1225-5475 (Print) 2093-7563 (Online)

Print publication date 31 May 2024

Received 02 May 2024 Revised 28 May 2024 Accepted 30 May 2024

DOI: https://doi.org/10.46670/JSST.2024.33.3.147

Energy-Efficient Ternary Modulator for Wireless Sensor Networks

Seunghan Baek¹^{, *} ; Seunghyun Son²^{, *} ; Sunmean Kim²^{, †}

1Department of Electrical Engineering, Pohang University of Science and Technology, 77 Cheongamro, Namgu, Pohang, Gyeongbuk, 37673, Korea
2School of Electronic and Electrical Engineering, Kyungpook National University, 80 Daehakro, Bukgu, Daegu, 41566, Korea

Correspondence to: ^† sunmean@knu.ac.kr ^*These authors equally contributed to this manuscript

This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License(https://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

Keywords:

WSNs, MVL, PSK, MTCMOS, Energy-efficient, Ternary, Modulator

1. INTRODUCTION

WSNs (Wireless Sensor Networks) are becoming increasingly important owing to their practical applications in various areas, as shown in Fig. 1 [1-5]. WSNs comprise sensor nodes and a network architecture. In these networks, sensor nodes are generally battery-powered, and the performance of these batteries directly affects the lifetime of the sensor network. Therefore, the power unit is an essential component, and energy issues are inevitable [6-7].

Fig. 1.

Applications of WSNs in various areas.

The total energy consumption of the entire network can be reduced by decreasing the energy usage of each sensor node. Several studies have been conducted to address this issue; however, most transmission standards in related research are based on binary transmission [8-12]. A recent study has suggested that a quaternary transmission scheme provides a more energy-efficient solution than a binary transmission scheme [13].

MVL (Multi-valued logic) data transmission consumes less power because fewer coded words will be used in data transmission [13]. Furthermore, MVL performs arithmetic operations faster than binary logic with fewer interconnections [14-15]. MVL systems can be realized using base three, base four, or other numeral bases. Ternary logic can be applied in phase shift keying (PSK). Modulator and demodulator are essential components to realize WSNs with PSK modulation as shown in Fig. 2. Baek et al. [16] proposed an energy-efficient ternary-to-binary (T2B) demodulator. Saha et al. [17] proposed a binary-to-ternary (B2T) modulator based on double pass-transistor Logic (DPL). However, owing to the structure of DPL circuits, where the logic gate must drive all the remaining parts, the previous modulator has weaknesses in energy efficiency. Kim et al. [18] proposed a logic synthesis methodology with a novel low-power circuit structure for ternary logic.

Fig. 2.

Components of sensor nodes in WSNs.

Optimizing the number of circuit elements and the power consumption in the modulator is vital in WSNs. This study proposes an energy-efficient 3-to-2 B2T modulator for the 8-ternary PSK, based on multi-threshold CMOS (MTCMOS). Our modulator converts 3-bit to 2-trit. Our design shows a significant improvement compared to previous design, demonstrating a remarkable decrease of 97.19% in the power-delay product (PDP) and a considerable reduction of 71.69% in device counts. The main contributions of this study are as follows.

• An optimized B2T modulator is proposed with lower energy consumption, and reduced device counts compared with previous designs.
• The existing low-power structure is optimized for ternary logic to integrate with MTCMOS.
• The application of MVL data transmission is presented by applying ternary logic to PSK modulation.

The remainder of this paper is structured as follows. Section 2 presents the design of 3-to-2 B2T modulator for 8-ternary PSK. In Section 3, the simulation results of our design and the comparison with previous design are presented. Finally, section 4 presents the conclusions of the study.

2. PROPOSED DESIGN

We propose the design of 3-to-2 B2T modulator for 8-ternary PSK as shown in Fig. 3 (a). In 8-ternary PSK, two trits are used, which represent the phase. Fig. 3 (b) represents an 8-ternary PSK constellation plot. The plot is configured in a circular arrangement. Each point on the plot corresponds to one of the eight distinct phase states evenly spaced around the circle. These states were separated by 45°, as determined by dividing the full 360° circle by eight.

Fig. 3.

(a) 3-to-2 B2T modulator for 8-ternary PSK, (b) Constellation plot for 8-ternary PSK, (c) Thick-Tox MOSFET and thin-Tox MOSFET.

The main difference between the binary and ternary domains is the number of logic values. The binary domain uses two logic values. It represents ‘1’ as a V_DD state (1.8 V) and ‘0’ as a GND state (0 V). The ternary domain uses the following three logical values. It represents ‘2’ as a V_DD state (1.8 V), ‘1’ as a V_DD/2 state (0.9 V), and ‘0’ as a GND state (0 V). We use MTCMOS to represent these states. To implement the multi-threshold voltage, we use two different oxide thicknesses T_ox (i.e., thick-T_ox and thin-T_ox), as shown in Fig. 3 (c). The thick-T_ox MOSFET has a high threshold voltage (V_T) and is therefore turned off when the gate voltage is in the V_DD/2 state. In contrast, the thin-T_ox MOSFET has low V_T and, therefore, turns on when the gate voltage is at V_DD/2 state.

The primary function of the B2T modulator is to represent the V_DD/2 state. To realize this function, we create two signal paths as shown in Fig. 4 (a): the half V_DD path and the V_DD/GND path. Each path has pull-up and pull-down networks. On the half V_DD path, the pull-up and pull-down networks are used to drive the output node to the V_DD/2 state. In the V_DD/GND path, the pull-up network drives the output node to the V_DD state, whereas the pull-down network drives it to the GND state. We adopt the state-of-the-art design presented in [18], with pull-up and pull-down networks connected to the pass transistors to reduce power consumption. In pass transistors, threshold drop and body effect enable the energy-efficient design of ternary logic circuits by managing output voltage transition and retention [18]. A mid-T_ox, medium oxide thickness, MOSFET is used as a pass transistor in [18]. In our design, the thick-T_ox MOSFET, the key component for reducing the PDP, is used instead. This MOSFET has high V_T. Therefore, the off-current required to retain the output voltage at V_DD/2 is reduced, and the power consumption in the V_DD/2 state is also reduced.

Fig. 4.

(a) Structure of the 3-to-2 B2T modulator with two signal paths. (b) Two K-maps of ternary output X in Table 1. (VDD/GND path K-map and Half VDD path K-map)

For the operation of 3-to-2 B2T modulator, we form a truth table as shown in Table 1. The truth table derives two different K-maps in Fig. 4 (b): the V_DD/GND path K-map and the half V_DD path K-map. Fig. 4 (b) shows two K-maps of the ternary output X in Table 1. Red boxes and blue boxes are represented in each K-map to construct the pull-up/pull-down network in Fig. 4 (a). The blue boxes represent the SOP terms of the pull-down networks, and the red boxes represent the SOP terms of the pull-up networks. The method of matching the transistors is same with binary static logic gates. Fig. 5 shows the transistor-level schematic of the 3-to-2 B2T modulator. Fig. 6 shows the layout of the 3-to-2 B2T modulator.

Table 1.

Truth table of 3-to-2 B2T modulator mapped with 8-ternary PSK.

Fig. 5.

Schematic design of a 3-to-2 B2T modulator; (a) output X, (b) output Y, (c) INV.

Fig. 6.

Layout design of the 3-to-2 B2T modulator.

3. SIMULATION SETUP AND RESULTS

3.1 Simulation Setup

We use the CMOS 180 nm process with 1.8 V supply voltage. We design a schematic and layout of the modulator circuit, using the Cadence Virtuoso. We conduct Calibre DRC, LVS, and PEX. To obtain the circuit characteristics, we execute a post-layout simulation using Synopsys HSPICE with a parasitic RC. In the thin T_ox MOSFET, the width was set to 2.64um with a length of 180 nm. Conversely, in the thick T_ox MOSFET, the width was set to 2um with lengths of 300 nm for p-type MOSFET and 350 nm for n-type MOSFET. Transistor size tuning is required in some circuits for correct operation. Each input pattern, with a 10ns pulse width and 20ps transient time, is thoroughly verified. The load capacitance is 5f F. We demonstrate the stability of our modulator under variations through corner simulations using three model parameters, namely, TT, FF, and SS. We consider 10% voltage variation, including 1.8, 1.98, 1.62 V along with three temperatures of -40, 25, and 125^oC.

3.2 Simulation Results

The waveform of the 3-to-2 B2T modulator is presented in Fig. 7, demonstrating that our design functions well and no data is lost during data conversion. The characteristics of the B2T modulator are listed in Table 2. We evaluated the design in [17] using self-implementation, and the results are listed in Table 3. Our design has smaller overheads in terms of power, delay, and area than the previous design. Corner simulations in our circuit demonstrate stability against PVT variations. Our design exhibits a reduction in PDP by 97.19% and in device counts by 71.69% compared to those with the previous design.

Fig. 7.

Waveform of proposed 3-to-2 B2T modulator including PVT corner simulation.

Table 2.

Characteristics of proposed 3-to-2 B2T modulator.

Table 3.

Result comparison with the previous design

4. CONCLUSIONS

In this study, we proposed an energy-efficient 3-to-2 B2T modulator for 8-ternary PSK, based on MTCMOS. By replacing the mid-T_ox MOSFET used as a pass transistor with thick-T_ox MOSFET, we optimized the low-power ternary logic structure in [18] to integrate with MTCMOS. We proved that our modulator is more efficient than the previous modulator in terms of energy consumption. We reduced PDP by 97.19% and device counts by 71.69% with our current design compared with the previous design. Our design, exhibiting energy-efficient performance, is ideal for use in sensor node. By reducing the energy consumption in the sensor nodes that constitute WSNs, we expect that our modulator will enhance the performance and lifespan of WSNs. Our future work includes analyzing the comprehensive impact of applying our modulator in various wireless sensor network environments.

Acknowledgments

This study was supported by Kyungpook National University Research Fund, 2024.

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