Editorial Board

Currently, customer demands for CMOS image sensor (CIS)-based applications are growing rapidly [1,2]. In particular, multiple CISs are mounted as electronic eyes on personalized portable devices such as mobile phones and healthcare applications. Because such electronic devices are mostly powered by batteries, maintaining low power consumption has become an important design issue for imaging sensor systems.

For analog-to-digital (A/D) conversion of signals, there are various types of readout analog-to-digital converters (ADCs): single-slope (SS) ADC, sigma-delta (Σ-Δ) ADC, successive approximate register (SAR) ADC, and cyclic (CY) ADC [3]-[6]. Among them, the SAR ADC has been in the spotlight for low-power readout because it does not consume static power. However, its capacitive digital-to-analog converter (C-DAC) for generating a full A/D reference requires a large area, making it difficult to design a layout in a narrow column pitch. Moreover, because the pixel pitch becomes smaller for high pixel resolution, the same problem is encountered in other types of column-parallel (CP) readout ADCs. Here, the pixel pitch is equal to the column pitch in the CP readout structure. To overcome this disadvantage, multi-column-parallel (MCP) readout structures in which one readout ADC covers several columns have been reported [7-9].

Recently, in addition to the studies on traditional circuit techniques for low-power design, various studies [8-11] utilizing the characteristics of the input signal have been reported to obtain further performance improvement. In a previous work [8], based on the image properties, a delta readout scheme that reads only the signal difference between two adjacent pixels (Δ_px) has been proposed for a power-efficient readout with SAR ADCs. After completing the A/D conversion for the previous pixel by utilizing its most significant bits (MSBs) MSB information, the C-DAC of the SAR ADC is not fully reset; only the remaining least signal bits (LSBs) are reset. MSBs are memorized and then re-switched in C-DAC for the next A/D conversion. Because the MSB information from the previous pixel is highly correlated with a selected pixel, the number of conversion steps is effectively reduced, resulting in a low-power readout.

In this work, with the same motivations as previous studies, we propose a more optimized delta readout algorithm for rolling-shutter readout CISs adopting the MCP readout structure. Compared to prior studies [8,9], this work considers the row-to-row correlation when changing the row to readout the pixel information (as in rolling shutter readout mechanism). Furthermore, depending on the readout timings, the power saving effect is maximized by effectively controlling the static bias current of a pre-amplifier in the proposed SAR ADC.

The remainder of this paper is organized as follows: Section 2 describes the circuit design issues of the proposed low-power imaging sensors with an advanced delta readout scheme. The measured results and discussions about the proposed CIS are presented in Section 3, followed by the conclusion in Section 4.

Fig. 8 shows a photograph of the testing CIS board with a microphotograph of the prototype chip. The chip was fabricated using a 0.18-μm CMOS process. A 160 × 120 pixel array with 4.4 μm pitch was implemented with 10 MCP readout channels, in which one SAR ADC covers 16 columns of pixels. The testing CIS board comprises a chip board and a field-programmable gate array (FPGA) board. The fabricated CIS chip was bonded to the chip board. To verify the performance of the prototype CIS, various types of control signals were generated by an external FPGA and supplied to the chip board by the FPGA board. The output codes of the chip board were transmitted to the PC through the USB interface and processed using a software program to display the real-time imaging on the screen. The capturing software program with various verification functions was customized using MATLAB programming.

Fig. 8. 
Photograph of the measurement environment with the microphotograph of the prototype chip.

A sample image captured by the prototype CIS is shown in Fig. 9. The prototype CIS demonstrated a frame rate of 120 frame per second (fps) with a total power consumption of 1.92 mW. In the dark illumination condition, as in [14], 100 frames were captured to obtain the standard deviation of noise, resulting in 0.47 LSB_rms, corresponding to 413.1 μV_rms. The 10-bit SAR ADC has the full input range of approximately 0.9 V with 1-LSB of 880 μV. A fixed-pattern noise from the MCP readout pattern was removed using off-chip digital calibration [8,9]. The pixel rate of the prototype CIS is approximately 2.3 mega pixel per second (Mp/s). With the proposed biasing control method, compared to the conventional MCP readout, a power saving effect of 10.6% was confirmed in this study. The measured performance of the prototype CIS is summarized in Table 1.

Fig. 9. 
Captured sample image from the prototype CIS.

The figure of merit (FoM) in terms of power efficiency and noise performance [15,16] is calculated as

From this, the developed CIS obtained an FoM of 344.3 μV·nJ. Table 2 shows the performance comparison with other works based on the 3T-APS pixel array. In terms of noise performances, it was confirmed that coupling noises between neighboring columns occurred owing to insufficient shielding. With further addition of the layout shielding pattern, the random noise will be reduced, resulting in further improved FoM. The measured performance of the prototype CIS is summarized in Table 1.

One of the layout issues in this work is that the input of the test ADC is laid without considering shielding across the global digital logic and timing generator, as shown in Fig. 10. Therefore, it is difficult to evaluate the performance of the designed ADC alone, such as differential non-linearity (DNL), integral non-linearity (INL), and readout noise. This problem is expected to be solved sufficiently by modifying the layout pattern.

Fig. 10. 
Cross-talk issue with digital logic and test input.

In this study, we proposed a delta readout SAR ADC optimized in the MCP readout structure. By alternating the MCP readout direction between the even and odd rows, additional memory for the row-to-row delta readout was not required, resulting in a reduced area of occupation. In addition, by applying different bias currents of a pre-amplifier according to the operating period, the power efficiency was improved compared to the previous work. This work is meaningful in that it overcomes the shortcomings of previous studies.